PXD20RM Datasheet, PDF (1463/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

VDDM
T1
T3
VDDM
T5
T7
COSP
T2
COSM
T4
SINP
T6
SINM
T8
VSSM
VSSM
Figure 42-16. Current flow for Integration (STEP = 2, ITGDCL = 1)
Figure 42-17 below shows that the sine coil is driven for STEP = 3 in reverse direction with respect to
STEP = 1 (M -> P direction). Again the other coil (cosine) is isolated from the analog supply voltages
because it is the integration phase of the current BIS.
VDDM
VDDM
T1
T3
T5
T7
COSP
T2
COSM
T4
SINP
T6
SINM
T8
VSSM
VSSM
Figure 42-17. Current flow for Integration (STEP = 3, ITGDCL = 1)
42.6.2 Setting of the PRESCALE Register
42.6.2.1 Timing Resolution Considerations
Set the ACDIV bits to the lowest division factor possible, resulting in the highest possible clock frequency
for the integration accumulator. This will give the most precise result.
PXD20 Microcontroller Reference Manual, Rev. 1
42-25