PXD20RM Datasheet, PDF (392/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 11-34. Mask parameter error status register field descriptions (continued)
Field
13
M_RLE_ERR
28
M_L3_parr_err
29
M_L2_parr_err
30
M_L1_parr_err
31
M_L0_parr_err
Mask the interrupt
1’b1: mask the interrupt
1’b0: Do not mask interrupt
Mask the interrupt
1’b1: mask the interrupt
1’b0: Do not mask interrupt
Mask the interrupt
1’b1: mask the interrupt
1’b0: Do not mask interrupt
Mask the interrupt
1’b1: mask the interrupt
1’b0: Do not mask interrupt
Mask the interrupt
1’b1: mask the interrupt
1’b0: Do not mask interrupt
Description
11.3.4.30 THRESHOLD_INP_BUF_1 Register
Figure 11-40 shows the threshold register for input buffer.
Offset: 0x234
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0
W
INP_BUF_P2_HI
0
INP_BUF_P2_LO
Reset 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
W
INP_BUF_P1_HI
0
INP_BUF_P1_LO
Reset 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Figure 11-40. Threshold input buffer 1 Register (THRESHOLD_INP_BUF_1)
Table 11-35. THRESHOLD_INP_BUF_1 field descriptions
Field
Description
INP_BUF_P2_HI High threshold for input buffer for blend stage 2.
INP_BUF_P2_LO Low threshold for input buffer for blend stage 2.
INP_BUF_P1_HI High threshold for input buffer for blend stage 1 (background).
INP_BUF_P1_LO Low threshold for input buffer for blend stage 1 (background plane).
11-58
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor