PXD20RM Datasheet, PDF (209/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

8.3.3.1.3 Output Clock Division Select Register (CGM_OCDS_SC)
Address 0xC3FE_0374
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0
SELDIV
W
SELCTL
00000000
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-5. Output Clock Division Select Register (CGM_OCDS_SC)
This register is used to select the current output clock source and by which factor it is divided before being
delivered at the output clock.
Table 8-6. Output Clock Division Select Register (CGM_OCDS_SC) Field Descriptions
Field
Description
SELDIV
Output Clock Division Select
00 output selected Output Clock without division
01 output selected Output Clock divided by 2
10 output selected Output Clock divided by 4
11 output selected Output Clock divided by 8
SELCTL Output Clock Source Selection Control — This value selects the current source for the output clock.
0000 16 MHz int. RC osc.
0001 4-16 MHz ext. xtal osc.
0010 primary PLL/2
0011 secondary PLL
0100 128 kHz int. RC osc.
0101 32 kHz ext. xtal osc.
0110 reserved
0111 RTC clock
1000 system clock
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-13