PXD20RM Datasheet, PDF (234/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

8.5.2 Overview
The FMPLLs enable the user to generate high speed system clocks from a common 4 MHz to 120 MHz
input clock. Further, the FMPLLs support programmable frequency modulation of the system clock. The
PLL multiplication factor, output clock divider ratio are all software configurable.
NOTE
The user must take care not to program device with frequency higher than
allowed (no hardware check).
The FMPLL’s block diagram is shown in Figure 8-30.
FXOSC
IDF
DIV2
MODE
BUFFER
Charge
Pump
Low Pass
Filter
NDIV
Loop
Frequency
Divider
VCO
Figure 8-30. FMPLL block diagram
ODF
PHI
DIV4
MODE
8.5.3 Features
Each FMPLL has the following major features:
• Input clock frequency from 4 MHz to 120 MHz
• Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
• Frequency modulated PLL
— Modulation enabled/disabled through software
— Triangle wave modulation
• Programmable modulation depth
— ±0.25% to ±4% deviation from center spread frequency
— –0.5% to –8% deviation from down spread frequency
— Programmable modulation frequency dependent on reference frequency
• Self-clocked mode (SCM) operation
• Five available modes
— Normal mode
— Progressive clock switching
— Normal Mode with SSCG
— Powerdown mode
— 1:1 mode (FMPLL0 only)
8-38
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor