PXD20RM Datasheet, PDF (1370/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Figure gives an example of the DDS mode in action.
Volume
Inter-Note
no-output-Time
Tone(0)
Tone(1)
Tone(n)
Duration
Figure 39-42. DDS Mode for one Channel
Time
39.7.2.4 Updating the configuration buffers
In DDS mode, the configuration registers for DDS mode, SGMCFG (upper word), DDSCH3/2/1/0,
ECRACH3/2/1/0, ECRRCH3/2/1/0, ECRSCH3/2/1/0, NTCH3/2/1/0, TPCCH3/2/1/0, are equipped with
hardware buffers.
If sound generation hasn’t started, the buffer values will be updated from the configuration registers every
IPS clock cycle.
When a note is being generated, the values of the configuration registers are copied to the buffers when
the following sequence is detected:
1. Configure the 1st note before starting the generation.
1. Setting the start of generation bit (SOGCHx bit in SGMCTL).
2. Buffers are updated at next IPS clock.
3. Synchronous reload occurs :
• at the end of Release phase if the no-output phase insertion is disabled.
• at the end of no-output phase, if the no-output phase insertion is enabled.
Up to the next reload, configuration registers and buffers can hold different values. The following figure
shows an example (not to scale).
39-46
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor