PXD20RM Datasheet, PDF (1241/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• Read address of the serial flash into QSPI_SFAR, refer to Section 35.4.4.4, Serial Flash Address
Register (QSPI_SFAR),. For IP Commands not related to specific addresses the base address of the
related flash need to be programmed.
• Instruction code options belonging to the IP Command into the QSPI_ICR[ICO] field.
• Instruction code belonging to the IP Command into the QSPI_ICR[IC] field.
Note that the write into the QSPI_ICR[IC] field must be the last step of the sequence. It is possible
to combine both fields of the QSPI_ICR into one single write. Refer to Section 35.4.4.5, Instruction
Code Register (QSPI_ICR), for details.
Note that there are some conditions were no IP Command is executed after writing the QSPI_ICR[IC] field
and the write operation itself is ignored. They are described in Section 35.6.4, Command arbitration.
35.5.3.1.2 AHB Commands
Note that the required components of the AHB commands are located in different registers w.r.t. the IP
Commands. They need to be written into the QSPI_ACR register like described in Section 35.4.4.11,
AMBA Control Register (QSPI_ACR).
The AHB Command itself is triggered by a read access of the host into the memory mapped serial flash
data, like described in Section 35.4.5.2, Memory Mapped Serial Flash Data - Individual Flash Mode on
Flash A.
Again the possible error conditions are described in Section 35.6.4, Command arbitration.
35.5.3.2 Flash Programming
In all cases the memory sector to be written needs to be erased first. The programming sequence itself is
then initiated in the following way:
1. Check that the TX Buffer is empty. If the QSPI_SFMSR[TXNE] bit is set the TX Buffer must be
cleared by writing 1 into the QSPI_MCR[CLR_TXF] bit.
2. Program the address related to the command in the QSPI_SFAR register. Optionally one can clear
the QSPI_TBSR[TRCTR] field by writing 1 into QSPI_MCR[CLR_TXF].
3. Provide initial data for the program command into the circular buffer via register TX Buffer Data
Register (QSPI_TBDR). At least one word of data must be written into the TX Buffer.
4. Program the required instruction code options (i.e. size of data) into the QSPI_ICR[ICO] register.
5. Trigger the IP Command to program the serial flash device by writing the instruction code into the
QSPI_ICR[IC] register.
6. Depending from the amount of data required step 3 must be repeated until all the required data have
been written into the QSPI_TBDR register. At any time the QSPI_TBDR[TRCTR] field can be
read to check how many words have been written actually into the TX Buffer.
Steps 4 and 5 may be executed together.
Upon writing the QSPI_ICR[IC] field (refer to step 5) the QuadSPI module will start to execute the
command by transferring instruction code, address and then data to the external device. The data are
fetched from the TX Buffer. It consists of 15 entries with 32-bit and is organized as a circular FIFO, whose
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
35-31