PXD20RM Datasheet, PDF (630/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

15.2.1.2 Integer Unit Features
The integer units feature support for single-cycle execution of most integer instructions, as follows:
• 32-bit AU for arithmetic and comparison operations
• 32-bit LU for logical operations
• 32-bit priority encoder for count-leading-zeros function
• 32-bit single-cycle barrel shifter for static shifts and rotates
• 32-bit mask unit for data masking and insertion
• Divider logic for signed and unsigned divide in  14 clock cycles with minimized execution timing
(integer unit 1 only)
• Pipelined 32  32 hardware multiplier array supports 32  3232 multiply with 2 clock latency,
1 clock throughput
15.2.1.3 Load/Store Unit Features
The load/store unit supports load, store, and load multiple/store multiple instructions by means of the
following:
• 32-bit effective address adder for data memory address calculations
• Pipelined operation supports throughput of one load or store operation per cycle
• Dedicated 64-bit interface to memory supports saving and restoring of up to two registers per cycle
for load multiple and store multiple word instructions
• Two-cycle load latency
• Big- and little-endian support
• Misaligned access support
15.2.2 L1 Cache Features
The L1 cache features the following:
• 4 KB, 2- or 4-way configurable set-associative instruction cache
• 64-bit data, 32-bit address bus plus attributes and control
• 32-byte line size
• Cache line locking
• Way allocation
• Tag and data parity or multi-bit EDC protection with correction/auto-invalidation capability
• Virtually indexed, physically tagged
• Pseudo round-robin replacement algorithm
• Line-fill buffer
• Hit under fill
15-4
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor