PXD20RM Datasheet, PDF (1589/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

49.4.2.1 NMI Status Flag Register (NSR)
This register holds the non-maskable interrupt status flags.
Address:0x0000
0
1
2
3
4
5
6
7
8
R _{NIF NOVF 0}
0
0
0
0
0
0
W _{w1c w1c}
Reset ₀
0
0
0
0
0
0
0
0
Access: User read/write (write 1 to clear)
9
10 11 12 13 14 15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31
R₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 49-3. NMI Status Flag Register (NSR)
Table 49-3. NSR Field Descriptions
Field
0
NIF
1
NOVF
Description
NMI Status Flag
This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (NREE or NFEE set),
NIF causes an interrupt request.
1 An event as defined by NREE and NFEE has occurred
0 No event has occurred on the pad
NMI Overrun Status Flag
This flag can be cleared only by writing a 1. Writing a 0 has no effect. It will be a copy of the current
NIF value whenever an NMI event occurs, thereby indicating to the software that an NMI occurred
while the last one was not yet serviced. If enabled (NREE or NFEE set), NOVF causes an interrupt
request.
1 An overrun has occurred on NMI input
0 No overrun has occurred on NMI input
49.4.2.2 NMI Configuration Register (NCR)
This register holds the configuration bits for the non-maskable interrupt settings.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
49-5