PXD20RM Datasheet, PDF (199/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

8.2 Auxiliary clocks
This device has five auxiliary clocks configurable using the MC_CGM registers. These auxiliary clocks
allow the associated peripherals to operate at clock speeds independent of the system clock (sys_clk). The
peripherals also use the undivided system clock to synchronously interface with the rest of the device. The
auxiliary clock configuration is:
• Auxiliary Clock 0: DCU3
• Auxiliary Clock 1: eMIOS0
• Auxiliary Clock 2: eMIOS1
• Auxiliary Clock 3: QuadSPI
• Auxiliary Clock 4: DCULite
8.3 Clock Generation Module (MC_CGM)
8.3.1 Introduction
This document describes the Clock Generation Module (MC_CGM) which includes, but is not limited to,
the functionality, pin description, and registers of the MC_CGM module.
8.3.1.1 Overview
The clock generation module (MC_CGM) generates reference clocks for all the SoC blocks. The
MC_CGM selects one of the system clock sources to supply the system clock. The MC_ME controls the
system clock selection (see the MC_ME documentation for more details). A set of MC_CGM registers
controls the clock dividers which are used for divided system and peripheral clock generation. The
MC_CGM memory space also includes the control registers of the clock sources themselves, for example
PLLs, IRCs, and oscillators. The MC_CGM also selects and generates an output clock.
Figure 8-2 depicts the MC_CGM block diagram.
PXD20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
8-3
Preliminary—Subject to Change Without Notice