PXD20RM Datasheet, PDF (832/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 21-11. PFCRP0 and PFCRP1 field descriptions (continued)
Field
Description
PFLIM[1:0]
PFLASH Prefetch Limit. Controls the prefetch algorithm used by the PFLASH prefetch controller. This field
defines a limit on the maximum number of sequential prefetches that are attempted between buffer misses. In all
situations when enabled, only a single prefetch is initiated on each buffer miss or hit. This field is cleared by
hardware reset.
00 No prefetching or buffering is performed.
01 The referenced line is prefetched on a buffer miss, i.e., prefetch on miss.
1x the referenced line is prefetched on a buffer miss, or the next sequential line is prefetched on a buffer hit (if
not already present), i.e., prefetch on miss or hit.
BFEN
PFLASH Line Read Buffers Enable. Enables or disables line read buffer hits. It is also used to invalidate the
buffers. This bit is cleared by hardware reset.
0 The line read buffers are disabled from satisfying read requests, and all buffer valid bits are cleared.
1 The line read buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when the buffers
are successfully filled.
21.3.2.9 Platform Flash Access Protection Register (PFAPR)
Offset: FLASH_REGS_BASE + 0x0024
R
W
Reset
0
1
M7AP
*
*
2
3
M6AP
*
*
4
5
M5AP
*
*
6
7
M4AP
*
*
8
9
M3AP
*
*
10
11
M2AP
*
*
Access: User read/write
12
13
14
15
M1AP
M0AP
*
*
*
*
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
SHSACC
W
0
0
0
0
SHDACC
0
0
0
0
Reset *
*
*
*
0
0
0
0
*
*
*
*
0
0
0
0
* = Initialized by hardware reset
Figure 21-12. PFlash Access Protection Register (PFAPR)
Table 21-12. PFAPR field descriptions
Field
MnAP
Description
Master n Access Protection. These fields are used to control whether read and write accesses to the flash
memory are allowed based on the master ID of a requesting master.
00 No accesses may be performed by this master.
01 Only read accesses may be performed by this master.
10 Only write accesses may be performed by this master.
11 Both read and write accesses may be performed by this master.
Note: For a list of master IDs, see the MnPFE field description in Table 21-11.
21-20
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor