PXD20RM Datasheet, PDF (1052/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Since the MPU_RGDAACn register is simply another memory mapping for MPU_RGDn.Word2, the field
definitions shown in Table 28-9 are identical to those presented in Table 28-7.
Table 28-9. MPU_RGDAACn Field Descriptions
Field
Description
0
M7RE
1
M7WE
2
M6RE
3
M6WE
4
M5RE
5
M5WE
6
M4RE
7
M4WE
8
M3PE
9–10
M3SM
11–13
M3UM
14
M2PE
15–16
M2SM
Bus master 7 read enable. If set, this flag allows bus master 7 to perform read operations. If cleared, any
attempted read by bus master 7 terminates with an access error and the read is not performed.
Bus master 7 write enable. If set, this flag allows bus master 7 to perform write operations. If cleared,
any attempted write by bus master 7 terminates with an access error and the write is not performed.
Bus master 6 read enable. If set, this flag allows bus master 6 to perform read operations. If cleared, any
attempted read by bus master 6 terminates with an access error and the read is not performed.
Bus master 6 write enable. If set, this flag allows bus master 6 to perform write operations. If cleared,
any attempted write by bus master 6 terminates with an access error and the write is not performed.
Bus master 5 read enable. If set, this flag allows bus master 5 to perform read operations. If cleared, any
attempted read by bus master 5 terminates with an access error and the read is not performed.
Bus master 5 write enable. If set, this flag allows bus master 5 to perform write operations. If cleared,
any attempted write by bus master 5 terminates with an access error and the write is not performed.
Bus master 4 read enable. If set, this flag allows bus master 4 to perform read operations. If cleared, any
attempted read by bus master 4 terminates with an access error and the read is not performed.
Bus master 4 write enable. If set, this flag allows bus master 4 to perform write operations. If cleared,
any attempted write by bus master 4 terminates with an access error and the write is not performed.
Bus master 3 process identifier enable. If set, this flag specifies that the process identifier and mask
(defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region
hit evaluation does not include the process identifier.
Bus master 3 supervisor mode access control. This 2-bit field defines the access controls for bus master
3 when operating in supervisor mode. The M3SM field is defined as:
0b00 r, w, x = read, write and execute allowed
0b01 r, –, x = read and execute allowed, but no write
0b10 r, w, – = read and write allowed, but no execute
0b11 Same access controls as that defined by M3UM for user mode
Bus master 3 user mode access control. This 3-bit field defines the access controls for bus master 3
when operating in user mode. The M3UM field consists of three independent bits, enabling read, write
and execute permissions: {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an
attempted access of that mode may be terminated with an access error (if not allowed by any other
descriptor) and the access not performed.
Bus master 2 process identifier enable. If set, this flag specifies that the process identifier and mask
(defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region
hit evaluation does not include the process identifier.
Bus master 2 supervisor mode access control. This 2-bit field defines the access controls for bus master
2 when operating in supervisor mode. The M2SM field is defined as:
0b00 r, w, x = read, write and execute allowed
0b01 r, –, x = read and execute allowed, but no write
0b10 r, w, – = read and write allowed, but no execute
0b11 Same access controls as that defined by M2UM for user mode
28-14
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor