PXD20RM Datasheet, PDF (1301/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 37-9. Functional Event Short Sequence Register (RGM_FESS) Field Descriptions (continued)
Field
Description
SS_CMU0_F Short Sequence for CMU0 clock frequency higher/lower than reference
HL
0 The reset sequence triggered by a CMU0 clock frequency higher/lower than reference event will start from
PHASE1
1 The reset sequence triggered by a CMU0 clock frequency higher/lower than reference event will start from
PHASE3, skipping PHASE1 and PHASE2
SS_CMU0_
OLR
Short Sequence for FXOSC frequency lower than reference
0 The reset sequence triggered by a FXOSC frequency lower than reference event will start from PHASE1
1 The reset sequence triggered by a FXOSC frequency lower than reference event will start from PHASE3,
skipping PHASE1 and PHASE2
SS_FMPLL0 Short Sequence for FMPLL0 fail
0 The reset sequence triggered by a FMPLL0 fail event will start from PHASE1
1 The reset sequence triggered by a FMPLL0 fail event will start from PHASE3, skipping PHASE1 and PHASE2
SS_SOFT
Short Sequence for software reset
0 The reset sequence triggered by a software reset event will start from PHASE1
1 The reset sequence triggered by a software reset event will start from PHASE3, skipping PHASE1 and
PHASE2
SS_CORE Short Sequence for CPU reset
0 The reset sequence triggered by a CPU reset event will start from PHASE1
1 The reset sequence triggered by a CPU reset event will start from PHASE3, skipping PHASE1 and PHASE2
SS_JTAG
Short Sequence for JTAG initiated reset
0 The reset sequence triggered by a JTAG initiated reset event will start from PHASE1
1 The reset sequence triggered by a JTAG initiated reset event will start from PHASE3, skipping PHASE1 and
PHASE2
37.3.1.8 STANDBY Reset Sequence Register (RGM_STDBY)
Address 0xC3FE_401A
Access: Supervisor read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 37-9. STANDBY Reset Sequence Register (RGM_STDBY)
This register defines reset sequence to be applied on STANDBY mode exit. It can be accessed in read/write
in either supervisor mode or test mode. It can be accessed in read only in user mode.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
37-25