PXD20RM Datasheet, PDF (858/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

figuration data prefetching is disabled.
21.4.5.5 Buffer Invalidation
The line read buffers may be invalidated by clearing the PFCRPx[BFEN] bit, which also disables the
buffers. Software may then restore the PFCRPx[BFEN] bit to its previous state, and the buffers will have
been invalidated.
21.5 Initialization Information
A reset is the highest priority operation for the flash module and terminates all other operations.
The flash module uses reset to initialize register and status bits to their default reset values. If the flash
module is executing a program or erase operation (PGM and/or ERS = 1) and a reset is issued, the
operation is aborted and the module disables the high voltage logic without damage to the high voltage
circuits. Reset aborts all operations and forces the flash module into user mode ready to receive accesses.
After reset is requested, MCR[DONE] goes low, and remains low during reset and reset recovery. At the
end of reset recovery, MCR[DONE] transitions from a 0 to a 1.
After reset is negated, register reads may be done, although it should be noted that registers that require
updating from shadow information, or other inputs, may not read updated values until MCR[DONE]
transitions high.
During reset recovery, register writes are not allowed until the MCR[DONE] bit transitions high to indicate
reset recovery is completed.
21.6 Application information
21.6.1 Background
Flash array access is relatively slow compared to a full speed system clock based on the PLL. To prevent
wait states on every flash access, line buffers are implemented. While wait states are required between the
flash array and line buffer, no wait states are required between a line buffer and the system bus. For
example, if the CPU is accessing sequential instructions starting at location 0, the first 32 bits (one line)
fetched will require wait states. The number of wait states is based on system clock frequency. However,
subsequent instructions contained in that 128 bit line buffer can be accessed without wait states.
Furthermore, with prefetching configured, the next sequential instructions outside the current line buffer
can be prefetched to different line buffer. After fetching all the instructions in current line buffer, the next
instruction is fetched for the next line buffer without delay.
Prefetching only helps performance when sequential accesses typically occur, such as for instructions.
Since data typically is not arranged sequentially (except for perhaps graphic data) prefetching for data
generally is not recommended.
The flash module on this device has two ports. Port 0 is always connected to the CPU. Port 1 is connected
to the other non-CPU masters.
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor