PXD20RM Datasheet, PDF (1449/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 42-10. PRESCALE Register Field Description (continued)
Field
Description
5-4 OFFCNC - Offset Cancellation polarity flip select. Refer to Section 42.4.1.4.3, DC Offset Cancellation. for
details of the offset cancellation mechanism. The OFFCNC bits set the preset value of the internal counter
which determines the polarity flips during the integration phase.
The preset value is derived from the ITGCNTLD register value with the following divider factor:
00 0: Selected polarity remains unchanged for all the time of the integration phase.
01 2: 1st polarity switch (and possibly a succeeding one) occurs after [ITGCNTLD div 2] DCNT ticks.
10 4: 1st polarity switch and succeeding ones occur after [ITGCNTLD div 4] DCNT ticks.
11 8: 1st polarity switch and succeeding ones occur after [ITGCNTLD div 8] DCNT ticks.
If the ITGCNTLD register value cannot be divided by the required factor an additional polarity flip occurs
with a duration corresponding to the bits shifted out.
2-0 ACDIV - Accumulator Sample Clock Divider Select. The accumulator sample clock is derived from the bus
clock according to the formula
<accumulator sample clock> = <bus clock> / (8 * 2^ACDIV)
According to this formula the divider factors are:
000 8
001 16
010 32
011 64
100 128
101 256
110 512
111 1024
The first ITGACC register update occurs when (8 * 2^ACDIV) bus clocks have expired after the ITGST bit
has been set by the SSD block.
42.4 Functional Description
For all the descriptions given here it is assumed that the SSD block has gained exclusive control of the SM
coils and the analog block is enabled appropriately.
42.4.1 Main Building Blocks of the SSD
The functional description given in this chapter deals with the main functional blocks. It concentrates on
the description of the implemented functionality. Refer to Figure 42-1 for details.
42.4.1.1 Analog Block
An overview of the analog block of the SSD block is given in Figure 42-10 below. Additionally the most
important sub blocks of the digital part which are connected to the analog blocks are shown in order to
clarify the joint operation of the analog block and the digital part.
PXD20 Microcontroller Reference Manual, Rev. 1
42-11