PXD20RM Datasheet, PDF (1539/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 46-29. Bit mapping example B (continued)
data signal
Remapped RGB[22]
Remapped RGB[21]
Remapped RGB [20:16]
Remapped RGB[15]
Remapped RGB[14]
Remapped RGB[13]
Remapped RGB [12:8]
Remapped RGB[7]
Remapped RGB[6]
Remapped RGB[5]
Remapped RGB [4:0]
Rising of pix_clk
B5
B3
0
G7
G5
G3
0
R7
R5
R3
0
Falling of pix_clk
B4
B2
0
G6
G4
G2
0
R6
R4
R2
0
c. TTL mode, below settings will remap the bit order as in Table 46-30
TCON_CTRL1.DATA_MODE = 0; //TTL mode
TCON_BMC.COLOR_ORDER = 3’b000; //color order RGB
TCON_BMC.BIT_ORDER = 1; //0 up to MSB7
TCON_CTRL1.COLOR_DEPTH = 1; //6bit per color;
Table 46-30. Bit mapping example C
RSDS 8-bits
Remapped RGB[23:16]
Remapped RGB[15:8]
Remapped RGB[7:0]
Rising of pix_clk
{R2,R3,R4,R5,R6,R7,2’b0}
{G2,G3,G4,G5,G6,G7,2’b0}
{B2,B3,B4,B5,B6,B7,2’b0}
46.4.4.4 Clock mapping in RSDS mode
To aid board design, it has been made possible to assign the pixel clock output to any of the 13 RSDS
differential pairs, configured via TCON_BMC.CLK_POS (see Section 46.3.3.2, Bit Mapping Control
(TCON_BMC)). The flexible clock mapping in RSDS mode is shown in Table 46-31.
data_
out
0
1
0/1 CLK¹
2/3 ~4/4² CLK
Table 46-31. Clock mapping in RSDS mode
CLK_POS[4:0]
2
3
4
5
6
7
8
~4/4
~5/5
9
10 11 12
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
46-31