PXD20RM Datasheet, PDF (975/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 27-5. UART buffer structure
BDR
0
1
2
3
4
5
6
7
UART mode
Tx0
Tx1
Tx2
Tx3
Rx0
Rx1
Rx2
Rx3
For 16-bit frames, the lower 8 bits will be written in BDR0 and the upper 8 bits will be written in BDR1.
27.9.3 UART transmitter
In order to start transmission in UART mode, the UARTCR[UART] and UARTCR[TXEN] bits must be
set. Transmission starts when BDR0 (least significant data byte) is programmed. The number of bytes
transmitted is equal to the value configured by the UARTCR[TDFLTFC] field (see Table 27-18).
The Transmit buffer size is as follows:
• 4 bytes when UARTCR[WL1] = 0
• 2 half-words when UARTCR[WL1] = 1
Therefore, the maximum transmission that can be triggered is 4 bytes (2 half-words). After the
programmed number of bytes has been transmitted, the UARTSR[DTFTFF] flag is set. If the
UARTCR[TXEN] field is cleared during a transmission, the current transmission is completed, but no
further transmission can be invoked. The buffer can be configured in FIFO mode (mandatory when DMA
Tx is enabled) by setting UARTCR[TFBM].
The access to the BDRL register is shown in Table 27-6.
Table 27-6. BDRL access in UART mode
Access
Mode¹
Word length²
IPS operation result
Write Byte0
Write Byte1-2-3
Write Half-word0-1
Write Word
Write Byte0-1-2-3
Write Half-word0
Write Half-word1
Write Word
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
Byte
Byte
Byte
Byte
Half-word
Half-word
Half-word
Half-word
OK
IPS transfer error
IPS transfer error
IPS transfer error
IPS transfer error
OK
IPS transfer error
IPS transfer error
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
27-19