PXD20RM Datasheet, PDF (374/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 11-22. SYN_POL Field Descriptions (continued)
Field
INV_PDI_CLK
INV_PXCK
NEG
BP_VS
BP_HS
INV_CS
INV_VS
INV_HS
Description
Polarity change of PDI input Clock.
1’b0: DCU3 samples data on the rising edge
1’b1: DCU3 samples data on the falling edge
Polarity change of Pixel Clock.
1’b0: Display samples data on the falling edge
1’b1: Display samples data on the rising edge
Indicates if value at the output (pixel data output) needs to be negated.
1’b0: Output is to remain same
1’b1: Output to be negated
Bypass Vertical Synchronize Signal (internal pin muxing).
1’b0: Do not bypass VSYNC signal output
1 ‘b1: CSYNC bypass VSYNC signal, output CSYNC instead of VSYNC
Bypass Horizontal Synchronize Signal (internal pin muxing).
1’b0: Do not bypass HSYNC signal output
1’b1: CSYNC bypass HSYNC signal, output CSYNC instead of HSYNC
Invert Composite Synchronize Signal.
1’b0: Not invert CSYNC signal, active HIGH
1 ‘b1: Invert CSYNC signal, active LOW
Invert Vertical Synchronize Signal
1’b0: Not invert VSYNC signal, active HIGH
1 ‘b1: Invert VSYNC signal, active LOW
Invert Horizontal Synchronize Signal.
1’b0: Not invert HSYNC signal, active HIGH
1’b1: Invert HSYNC signal, active LOW
11.3.4.18 Threshold Register
Figure 11-21 represents the Threshold Register.
Offset: 0x1E8
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0 0 0
W
LS_BF_VS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
OUT_BUF_HIGH
W
OUT_BUF_LOW
Reset 0 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0
Figure 11-21. Threshold Register
11-40
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor