PXD20RM Datasheet, PDF (587/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 13-4. Number of DRAM banks addressed and mapping of address to DRAM bank address (continued)
BKSEL
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Number of
banks
8
4
8
4
8
4
8
4
8
4
8
8
8
8
DRAM bank address
DRAM_BANK[2:0] = address[13:11]
DRAM_BANK[1:0] = address[13:12]
DRAM_BANK[2:0] = address[14:12]
DRAM_BANK[1:0] = address[14:13]
DRAM_BANK[2:0] = address[15:13]
DRAM_BANK[1:0] = address[15:14]
DRAM_BANK[2:0] = address[16:14]
DRAM_BANK[1:0] = address[25:24]
DRAM_BANK[2:0] = address[26:24]
DRAM_BANK[1:0] = address[26:25]
DRAM_BANK[2:0] = address[27:25]
DRAM_BANK[2:0] = address[28:26]
DRAM_BANK[2:0] = address[29:27]
DRAM_BANK[2:0] = address[30:28]
Table 13-5. Mapping of address to DRAM column address
B16
DRAM column address
0
DRAM_COLUMN = {address[13:3], 1’b0}
1
DRAM_COLUMN = {address[12:3], 2’b0}
NOTE
In 16-bit mode (16BITMODE = 1), DDR memories with column address
line 0 to 7 are not supported.
Table 13-6. Mapping of address to DRAM row address
ROWSEL
0
1
2
3
4
5
6
7
DRAM row address
DRAM_ROW[15:0] = address[25:10]
DRAM_ROW[15:0] = address[26:11]
DRAM_ROW[15:0] = address[27:12]
DRAM_ROW[15:0] = address[28:13]
DRAM_ROW[15:0] = address[29:14]
DRAM_ROW[15:0] = address[30:15]
DRAM_ROW[14:0] = address[30:16]
DRAM_ROW[13:0] = address[24: 9]
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
13-7