PXD20RM Datasheet, PDF (868/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 22-7. GFX2D Stride Setting (GXGSTRIDE) Field Descriptions
Field
Description
2-0
STRIDE
Configuration of stride used by the GXG to match the setting applied to the GFX2D in an OpenVG driver.
3’b000 - 4096
3’b001 – 2048
3’b010 – 1024
3’b011 – 512
3’b100 – 256
3’b101 - 128
3’b110 - 64
22.4 Functional Description
22.4.1 IPS to AHB bridge
This bridge acts as an interface between the IP Skyblue specification and the AHB bus. The IPS signals
are connected to the AIPS block and the AHB signals are connected to the GFX2D 32-bit slave port.
A transfer error is asserted with an access to an IPS address offset greater than or equal to 0x800.
22.4.2 AXI to AHB bridge
This unidirectional bridge converts 64-bit AXI transactions into appropriate 64-bit AHB transactions and
handles the multiplexing of the data channels. It has an AXI slave port as an input port and an AHB-Lite
master port as an output port.
22.4.3 1x2 AXI bus matrix
The AXI bus matrix enables the GFX2D 64-bit master port to communicate with two AXI slave ports. It
has active transactions to only a single slave at a time and is responsible for forwarding all AXI
transactions in the same order that the transactions were initiated.
Table 22-8 shows the default parameter settings for the AXI bus matrix.
Table 22-8. Bus matrix default parameters
Slave Ports
Regions
Slave 0
00
(DRAM Controller)
01
02
03
Slave 1
10
(Cross Bar Switch)
11
12
13
Start Address
0x0000_0000
0x2000_0000
0xA000_0000
0xC000_0000
0x4000_0000
0x6000_0000
0x8000_0000
0x9000_0000
End Address
0x1FFF_FFFF
0x3FFF_FFFF
0xBFFF_FFFF
0xFFFF_FFFF
0x5FFF_FFFF
0x7FFF_FFFF
0x8FFF_FFFF
0x9FFF_FFFF
Mapped Regions
No
Yes
Yes
No
Yes
Yes
Yes
No
22-8
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor