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PXD20RM Datasheet, PDF (872/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller
During the data phase of write transactions, the 8-bit alpha component of each 32-bit pixel is suppressed,
and the byte strobes of partially written double-words (first and last double-words depending on
alignment) are masked.
Table 22-11 and Table 22-12 show the color depth conversion mapping. The GFX2D address shown is
relative to the FIRST address and the physical address shown is relative to the BASE address.
During the data phase of read transactions, the programmable 8-bit ALPHA constant is returned in the
alpha component byte lane. If MODE[1] is set to enable color depth conversion, MODE[0] indicates
which byte is the alpha component (first or last byte) in the 32-bit pixel value.
Table 22-11. Color Depth Conversion mapping (MODE[0] = 0)
Offset
64-bit GFX2D Data
Address [7:0] [15:8 [23:1 [31:2 [39:3 [47:4 [55:4 [63:5
] 6] 4] 2] 0] 8] 6]
0x00 R0 G0 B0 A0 R1 G1 B1 A1
0x08 R2 G2 B2 A2 R3 G3 B3 A3
0x10 R4 G4 B4 A4 R5 G5 B5 A5
0x18 R6 G6 B6 A6 R7 G7 B7 A7
—
—
0x50 R20 G20 B20 A20 R21 G21 B21 A21
0x58 R22 G22 B22 A22 R23 G23 B23 A23
0x60 R24 G24 B24 A24 R25 G25 B25 A25
0x68 R26 G26 B26 A26 R27 G27 B27 A27
—
—
0xE0 R56 G56 B56 A56 R57 G57 B57 A57
0xE8 R58 G58 B58 A58 R59 G59 B59 A59
0xF0 R60 G60 B60 A60 R61 G61 B61 A61
0xF8 R62 G62 B62 A62 R63 G63 B63 A63
Offset
64-bit Physical RAM Data
Address [7:0] [15:8 [23:1 [31:2 [39:3 [47:4 [55:4 [63:5
] 6] 4] 2] 0] 8] 6]
0x00 R0 G0 B0 R1 G1 B1 R2 G2
0x08 B2 R3 G3 B3 R4 G4 B4 R5
0x10 G5 B5 R6 G6 B6 R7 G7 B7
0x18 R8 G8 B8 R9 G9 B9 R10 G10
—
—
0x38 B18 R19 G19 B19 R20 G20 B20 R21
0x40 G21 B21 R22 G22 B22 R23 G23 B23
0x48 R24 G24 B24 R25 G25 B25 R26 G26
0x50 B26 R27 G27 B27 R28 G28 B28 R29
—
—
0xA8 R56 G56 B56 R57 G57 B57 R58 G58
0xB0 B58 R59 G59 B59 R60 G60 B60 R61
0xB8 G61 B61 R62 G62 B62 R63 G63 B63
0xC0 R64 G64 B64 R65 G65 B65 R66 G66
22-12
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor