PXD20RM Datasheet, PDF (1083/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

29.3.2.8 RESET Mode Configuration Register (ME_RESET_MC)
Address 0xC3FD_C020
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0 0 0 0 0 0 0 0 PDO 0 0
0 0 FLAON
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
00000000
SYSCLK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Figure 29-9. RESET Mode Configuration Register (ME_RESET_MC)
This register configures system behavior during RESET mode. Please refer to Table 29-11 for details.
29.3.2.9 TEST Mode Configuration Register (ME_TEST_MC)
Address 0xC3FD_C024
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
00000000
00
PDO
00
FLAON
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0
W
SYSCLK
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Figure 29-10. TEST Mode Configuration Register (ME_TEST_MC)
This register configures system behavior during TEST mode. Please refer to Table 29-11 for details.
NOTE
Byte write accesses are not allowed to this register.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
29-25