PXD20RM Datasheet, PDF (856/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

NOTE
In the event of an ECC error or Single Bit Correction, during the ECC Logic
Check (UTO[EIE] high), the ADR register will not be loaded, and the
address tagged to receive the UT0[DSI], UT1[DAI] and/or UT2[DAI]
values will be persevered.
6. Once completed, clear the UT0[EIE] bit to 0.
21.4.5 PFLASH2P
The PFLASH2P has two AHB-Lite slave ports and a single flash array interface. The dual ported design
of the PFLASH2P enables efficient use of a single flash memory array the CPU and other AHB masters.
Each AHB port has dedicated line buffers to support single-cycle read accesses and to limit accesses to the
flash array.
The PFLASH2P generates read and write enables, the flash array address, write size, and write data as
inputs to the flash array controller. The PFLASH2P captures read data from the flash array interface and
drives it onto the appropriate AHB port.
If line buffering is enabled, when data is read from the array it is stored in a line buffer. Up to four lines of
data (128 bits) are buffered by the PFLASH2P for each AHB port.
If pre-fetching is enabled, data is read in advance and stored in the line buffers allowing single-cycle (zero
AHB wait-states) read data responses on buffer hits. Prefetch triggering may be restricted to instruction
accesses only, data accesses only, or may be unrestricted. Prefetch triggering may also be controlled on a
per-master basis.
Arbitration between the two AHB ports for access to the flash interface is primarily based on the type of
access; writes have priority over reads which have priority over prefetches. If both ports are doing the same
type of access, priority is based on the settings of the arbitration and priority bits in the PFCRP0 register.
21.4.5.1 Line Read Buffers and Prefetch Operation
The PFLASH2P_H7Fb contains four read buffers per AHB port which are used to hold line and ECC data
read from the flash array. Each buffer operates independently, and is filled using a single array access. The
buffers are used for both prefetch and normal demand fetches.
Prefetch triggering is controllable on a per-master and access-type basis. Bus masters may be enabled or
disabled from triggering prefetches, and triggering may be further restricted based on whether a read
access is for instruction or data. A read access to the PFLASH2P_H7Fb may trigger a prefetch to the next
sequential line of array data on the cycle following the request. The access address is incremented to the
next-higher 16 byte boundary, and a flash array prefetch is initiated if the data is not already resident in a
line read buffer. Prefetched data is always loaded into the least-recently-used buffer.
Buffers may be in one of six states, listed here in prioritized order:
• Invalid - the buffer contains no valid data
• Used - the buffer contains valid data which has been provided to satisfy an AHB burst type read
• Valid - the buffer contains valid data which has been provided to satisfy an AHB single type read
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor