PXD20RM Datasheet, PDF (1242/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

read pointer is incremented after each fetch. When all data are transmitted, the QuadSPI module will return
from ‘busy’ to ‘idle’. However, this is not true for the external device since the internal programming is
still ongoing. It is up to the user to monitor the relevant status information available from the serial flash
device and to ensure that the programming is finished properly.
35.5.3.3 Flash Read
Host access to the data stored in the external serial flash device is done in two steps: First the data must be
read into the internal buffers and in the second step these internal buffers can be read by the host.
35.5.3.3.1 Reading Serial Flash Data into the QuadSPI Module
Read access to the external serial flash device can be triggered in two different ways:
• IP Command Read: For reading flash data into the RX Buffer the user must provide the
required components of the related SFM command, including the selection of the flash device and
the access mode, to the QSPI_SFAR and the QSPI_ICR registers. All available read commands
supported by the external serial flash are possible.
Optionally it is possible to clear the RX Buffer pointer prior to triggering the IP Command by
writing a 1 into the QSPI_MCR[CLR_RXF] bit.
From these inputs the complete transaction is built when the QSPI_ICR[IC] field is written. The
transaction related to the read access starts and the requested number of bytes is fetched from the
external serial flash device into the RX Buffer. Since the read access is triggered by an IP command
the IP_ACC status bit is set driving in turn the BUSY bit (both are located in the QSPI_SFMSR).
The communication with the external serial flash is stopped when the specified number of bytes
has been read (successful completion of the transaction).
• AHB Command Read: For reading flash data into the AHB Buffer the user must setup a read
access to the address range were the external serial flash devices are mapped to by programming
the QSPI_ACR register with the requested data not already available in the AHB Buffer. Flash
device selection and access mode are determined by the address accessed in the AHB address space
associated to the QuadSPI module, refer to Section 35.4.5.2, Memory Mapped Serial Flash Data -
Individual Flash Mode on Flash A, Section 35.4.5.3, Memory Mapped Serial Flash Data -
Individual Flash Mode on Flash B, and Section 35.4.5.4, Memory Mapped Serial Flash Data -
Parallel Flash Mode.
On each AHB read access to the memory mapped area the valid data in the AHB Buffer are
checked against the address requested in the actual read. When the AHB read request can’t be
served from the content of the AHB Buffer the complete transaction to access the external serial
flash device is built from the QSPI_ACR register contents and started. The requested number of
buffer entries defined in the QSPI_ACR[ARSZ] field is then fetched from the external serial flash
device into the internal AHB Buffer. Since the read access is triggered via the AHB bus the
QSPI_SFMSR[AHB_ACC] status bit is set driving in turn the QSPI_SFMSR[BUSY] bit until the
transaction is finished. The communication with the external serial flash is stopped when the
specified number of entries has been filled.
Basically the AHB buffer behaves similar to a cache memory with a size of one single line.
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor