PXD20RM Datasheet, PDF (264/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Name
Table 9-3. XBAR Register Summary (continued)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
AULB
Note: for n = 0 to 7
9.3.2 XBAR Register Descriptions
The following paragraphs provide detailed descriptions of the various XBAR registers.
Table 9-4 provides a key to the terms found in XBAR registers.
Table 9-4. Register Terms
Term
Gray bit
Access
S
—
Type
r
w
rw
rwm
w1c
slfclr
Reset
0
1
u
?
Description
Unimplemented bit; always reads as zero;writing has no effect
Supervisor mode only
Supervisor or user mode
Read only; writing to this bit has no effect
Write only
Standard read/write bit. Only software can change a bit’s value
(other than a hardware reset).
A read/write bit that may be modified by hardware in some fashion
other than reset.
A status bit that can be read and cleared by writing a logic 1
Self-clearing bit. Writing a 1 has some effect on module, but it
always reads as a 0.
Resets to a logic 0
Resets to a logic 1
Unaffected by reset
Reset state is unknown.
9.3.2.1 Master Priority Register
The Master Priority Register (MPR) sets the priority of each master port on a per slave port basis and
resides in each slave port.
PXD20 Microcontroller Reference Manual, Rev. 1
9-6
Freescale Semiconductor
Preliminary—Subject to Change Without Notice