PXD20RM Datasheet, PDF (274/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

A block diagram of a master port can be seen in Figure 9-6.
Capture Unit
Addr/Cntrl Addr/Cntrl
Async/Flopped_sel
Decoder
Addr/Cntrl
Next_slave_port[7:0]
Illegal_access
Decoder
Addr/Cntrl
Slave_port_rqst[7:0]
Request_enable
State Machine
Next_slave_port[7:0] Async/Flopped_sel
Illegal_access
Request_enable
Hready_in
Slv_hready[7:0]
Hready_out
Slv_hresp[7:0]
Hresp
Slv_is_mine[7:0]
Control_bits Rdata_sel
Registers
Read_sel
Write_sel
Wdata
Control_bits
Xfr_wait
Xfr_error
Rdata
Mux
Sel
Hrdata Slv_hrdata[7:0]
Figure 9-6. XBAR Master Port Block Diagram
9-16
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor