PXD20RM Datasheet, PDF (746/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

18.8.2.1 Time Base Generation
For the OPWFM with internal clock source operation mode, the internal counter rate can be modified by
configuring the clock prescaler ratio. Figure 18-38 shows an example of a time base with prescaler ratio
equal to one.
NOTE
MCB and OPWFMB modes have a different behavior.
PRE SCALED CLOCK RATIO = 1 (bypassed)
system clock
input event/prescaler clock enable = 1
see note 1
internal counter 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
match value = 3
FLAG set event
FLAG pin/register
FLAG clear
Note 1: When a match occurs, the first clock cycle is used to
clear the internal counter, starting another period.
Figure 18-38. Time base period when running in the fastest prescaler ratio
If the prescaler ratio is greater than one or external clock is selected, the counter may behave in three
different ways depending on the channel mode:
• If MC mode and Clear on Match Start and External Clock source are selected the internal counter
behaves as described in Figure 18-39.
• If MC mode and Clear on Match Start and Internal Clock source are selected the internal counter
behaves as described in Figure 18-40.
• If MC mode and Clear on Match End are selected the internal counter behaves as described in
Figure 18-41.
• If OPWFM mode is selected the internal counter behaves as described in Figure 18-40. The
internal counter clears at the start of the match signal, skips the next prescaled clock edge and then
increments in the subsequent prescaled clock edge.
NOTE
MCB and OPWFMB modes have a different behavior.
18-44
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor