PXD20RM Datasheet, PDF (640/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

16.1.1 Overview
The DMA is a highly-programmable data transfer engine, which has been optimized to minimize the
required intervention from the host processor. It is intended for use in applications where the data size to
be transferred is statically known, and is not defined within the data packet itself. The DMA hardware
supports:
• Single design supporting 16-channel implementation
• Connections to the AMBA-AHB crossbar switch for bus mastering the data movement, slave bus
for programming the module
— Parameterized support for 32- and 64-bit AMBA-AHB datapath widths
• 32-byte transfer control descriptor per channel stored in local memory
• 32 bytes of data registers, used as temporary storage to support burst transfers
Throughout this document, n is used to reference the channel number. Additionally, data sizes are defined
as byte (8-bit), halfword (16-bit), word (32-bit) and doubleword (64-bit).
16.1.2 Features
The DMA module supports the following features:
• All data movement via dual-address transfers: read from source, write to destination
— Programmable source, destination addresses, transfer size, plus support for enhanced
addressing modes
• Transfer control descriptor organized to support two-deep, nested transfer operations
— An inner data transfer loop defined by a “minor” byte transfer count
— An outer data transfer loop defined by a “major” iteration count
• Channel service request via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
– Independent channel linking at end of minor loop and/or major loop
— Peripheral-paced hardware requests (one per channel)
— For all three methods, one service request per execution of the minor loop is required
• Support for fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests
— One interrupt per channel, optionally asserted at completion of major iteration count
— Error terminations are optionally enabled per channel, and logically summed together to form
a small number of error interrupt outputs
• Support for scatter/gather DMA processing
• Support for complex data structures
• Support to cancel transfers via software or hardware
16-2
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor