SH7730 Datasheet, PDF (963/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 28 I/O Port
28.17 Port S
Port S is an input/output port with the pin configuration shown in figure 28.16. Each pin has an
input pull-up MOS, which is controlled by the port S control register (PSCR) in the PFC.
Port S
PTS4 (input/output)/SCIF2_RTS (output)/SIOF_SYNC (input/output)
PTS3 (input)/SCIF2_CTS (input)/SIOF_MCK (input) IRQ5 (input)
PTS2 (input/output)/SCIF2_TXD (output)/SIOF_TXD (output)
PTS1 (input)/SCIF2_RXD (input)/SIOF_RXD (input)
PTS0 (input/output)/SCIF2_SCK (input/output)/SIOF_SCK (input/output)
Figure 28.16 Port S
28.17.1 Port S Data Register (PSDR)
PSDR is a register that stores data for pins PTS4 to PTS0. Bits PS4DT to PS0DT correspond to
pins PTS4 to PTS0. For pins that function as general-purpose output pins, a read operation directly
reads out the value from this register. For pins that function as general-purpose input pins, a read
operation reads out the level on the corresponding pin.
Bit: 7
6
5
4
3
2
1
0
— — — PS4DT PS3DT PS2DT PS1DT PS0DT
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R/W R R/W R R/W
Bit
Bit Name
7 to 5 
4
PS4DT
3
PS3DT
2
PS2DT
1
PS1DT
0
PS0DT
Initial
Value R/W
All 0 R
0
R/W
0
R
0
R/W
0
R
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Table 28.18 shows the function of PSDR.
Rev. 1.00 Sep. 19, 2007 Page 915 of 1136
REJ09B0359-0100