SH7730 Datasheet, PDF (867/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 25 SIM Card Module (SIM)
25.3.1 Serial Mode Register (SCSMR)
SCSMR is an 8-bit readable/writable register that selects settings for the communication format of
the smart card interface.
Bit: 7
6
5
4
3
2
1
0
HOEN LCB PB WECC SDIR SINV RST SMIF
Initial value: 0
0
0
0
0
0
0
1
R/W: R/W R/W R/W R/W R/W R/W R/W R
Bit
7, 6
5
4
3 to 0
Bit Name

Initial
Value
All 0

1
O/E
0

All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R Reserved
This bit is always read as 1. The write value should
always be 1.
R/W Parity Mode
Selects whether even or odd parity is to be used when
adding a parity bit and checking parity.
0: Even parity*¹
1: Odd parity*²
Notes: 1. When set to even parity, during transmission
a parity bit is added such that the sum of 1
bits in the parity bit and transmit characters is
even.
During reception, a check is performed to
ensure that the sum of 1 bits in the parity bit
and the receive characters is even.
2. When set to odd parity, during transmission a
parity bit is added such that the sum of 1 bits
in the parity bit and transmit characters is odd.
During reception, a check is performed to
ensure that the sum of 1 bits in the parity bit
and the receive characters is odd.
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Sep. 19, 2007 Page 819 of 1136
REJ09B0359-0100