SH7730 Datasheet, PDF (320/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 10 Interrupt Controller (INTC)
10.5.2 Multiple Interrupts
When handling multiple interrupts, an interrupt handling routine should include the following
procedures:
1. To identify the interrupt source, branch to a specific interrupt handling routine for the interrupt
source by using the INTEVT code as an offset.
2. Clear the interrupt source in each specific interrupt handling routine.
3. Save SSR and SPC to the stack.
4. Clear the BL bit in SR. When the INTMU bit in CPUOPM is set to 1, the interrupt mask level
(IMASK) in SR is automatically modified to the level of the accepted interrupt. When the
INTMU bit in CPUOPM is cleared to 0, set the IMASK bit in SR by software to the accepted
interrupt level.
5. Handle the interrupt as required.
6. Set the BL bit in SR to 1.
7. Restore SSR and SPC from memory.
8. Execute the RTE instruction.
When these procedures are followed in order, an interrupt of higher priority than the one being
handled can be accepted if multiple interrupts occur after step 4. This reduces the interrupt
response time for urgent processing.
10.5.3 Interrupt Masking by MAI Bit
Setting the MAI bit in ICR0 to 1 masks interrupts while the NMI signal is low regardless of the
BL and IMASK bit settings in SR.
• Normal operation or sleep mode
All interrupts are masked while the NMI signal is low. Note that only NMI interrupts due to
NMI signal input occur.
• Standby mode
All interrupts including NMI are masked while the NMI signal is low. While the MAI bit is set
to 1, the NMI interrupt cannot be used to clear standby mode.
Rev. 1.00 Sep. 19, 2007 Page 272 of 1136
REJ09B0359-0100