SH7730 Datasheet, PDF (250/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
31
2019
14 13
87
210
Address field 1 1 1 1 0 1 1 1 0 0 0 0 _{* * * * * *}
E
* * * * * *⁰⁰
31 29 28
Data field
PPN
10 9 8 7 6 5 4 3 2 1 0
V PR C D
PPN: Physical page number
V: Validity bit
E: Entry
SZ: Page size bits
D: Dirty bit
*: Don't care
PR: Protection key data _SZ1
C: Cacheability bit
SH
WT
SH: Share status bit
WT: Write-through bit
: Reserved bits (write value should be 0
and read value is undefined )
Figure 7.23 Memory-Mapped UTLB Data Array (TLB Compatible Mode)
7.7.6 UTLB Data Array (TLB Extended Mode)
In TLB extended mode, the names of the data arrays have been changed from UTLB data array to
UTLB data array 1, UTLB data array 2 is added, and the EPR and ESZ bits are accessible. In TLB
extended mode, the PR and SZ bits of UTLB data array 1 are reserved and 0 should be specified
as the write value for these bits. In addition, when a write to UTLB data array 1 is performed, a
write to UTLB data array 2 of the same entry should always be performed after that.
In TLB compatible mode (MMUCR.ME = 0), UTLB data array 2 cannot be accessed. Operation if
they are accessed is not guaranteed.
(1) UTLB Data Array 1
In TLB extended mode, bits 7 to 4 in the data field, which correspond to the PR and SZ bits in
compatible mode, are reserved. Specify 0 as the write value for these bits.
31
20 19
14 13
Address field _{1 1 1 1 0 1 1 1 0 0 0 0 * * * * * *}
E
87
210
* * * * * *00
31 29 28
Data field
[Legend]
PPN: Physical page number
V: Validity bit
E: Entry
D: Dirty bit
*: Don't care
PPN
10 9 8 7
V
C: Cacheability bit
SH: Share status bit
WT: Write-through bit
: Reserved bits
(write value should be 0,
and read value is undefined)
43210
CD
SH WT
Figure 7.24 Memory-Mapped UTLB Data Array 1 (TLB Extended Mode)
Rev. 1.00 Sep. 19, 2007 Page 202 of 1136
REJ09B0359-0100