SH7730 Datasheet, PDF (458/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
12.3.2 DMA Source Address Registers (SARB_0 to SARB_3)
SARB are 32-bit readable/writable registers that specify the source address of a DMA transfer that
is set in SAR again in repeat/reload mode. Data to be written from the CPU to SAR is also written
to SARB. To set SARB address that differs from SAR address, write data to SARB after SAR.
To transfer data in word or in longword units, specify the address with word or longword address
boundary. When transferring data in 8-byte, 16-byte, or 32-byte units, an 8-byte, 16-byte, or 32-
byte boundary must be set for the source address value.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SARB
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SARB
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
12.3.3 DMA Destination Address Registers (DAR_0 to DAR_5)
DAR are 32-bit readable/writable registers that specify the destination address of a DMA transfer.
During a DMA transfer, these registers indicate the next destination address.
To transfer data in word or in longword units, specify the address with word or longword address
boundary. When transferring data in 8-byte, 16-byte, or 32-byte units, an 8-byte, 16-byte, or 32-
byte boundary must be set for the source address value.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DAR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Sep. 19, 2007 Page 410 of 1136
REJ09B0359-0100