SH7730 Datasheet, PDF (285/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 9 On-Chip Memory
Section 9 On-Chip Memory
This LSI includes the IL memory which is suitable for instruction storage.
9.1 Features
(1) IL Memory
• Capacity
The IL memory in this LSI is 16 Kbytes.
• Page
The IL memory is divided into four pages (pages 0, 1, 2, and 3).
• Memory map
The IL memory is allocated to the addresses shown in table 9.1 in both the virtual address
space and the physical address space.
Table 9.1 IL Memory Addresses
Page
Page 0
Page 1
Page 2
Page 3
Memory Size
16 Kbytes
H'E520 0000 to H'E520 0FFF
H'E520 1000 to H'E520 1FFF
H'E520 2000 to H'E520 2FFF
H'E520 3000 to H'E520 3FFF
• Ports
The page has three independent read/write ports and is connected to the SuperHyway bus, the
cache/RAM internal bus, and the instruction bus. The instruction bus is used when the IL
memory is accessed through instruction fetch. The cache/RAM internal bus is used when the
IL memory is accessed through operand access. The SuperHyway bus is used for IL memory
access from the SuperHyway bus master module.
• Priority
In the event of simultaneous accesses to the same page from different buses, the access
requests are processed according to priority. The priority order is: SuperHyway bus >
cache/RAM internal bus > instruction bus.
Rev. 1.00 Sep. 19, 2007 Page 237 of 1136
REJ09B0359-0100