SH7730 Datasheet, PDF (755/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
(5) Receiving Serial Data (Clock Synchronous Mode)
Figures 22.15 and 22.16 show sample flowcharts for receiving serial data. When switching
from asynchronous mode to clock synchronous mode without SCIF initialization, make sure
that the ORER bit in SCLSR and the PER and FER bits in SCFCR are cleared to 0.
Initialization
[1]
Start of reception
[1] Initialization of SCIF:
See figure 22.12, Sample Flowchart for
SCIF Initialization.
Read ORER flag in SCLSR
ORER = 1?
Yes
[2]
[2] Receive error handling:
Read the ORER flag in SCLSR to identify
any error, perform the appropriate error
handling, then clear the ORER flag to 0.
Reception cannot be resumed while the
ORER flag is set to 1.
No
Error handling
[3] SCIF status check and receive data read:
Read RDF flag in SCFSR
[3]
Read SCFSR and check that RDF = 1,
then read the receive data in SCFRDR,
and clear the RDF flag to 0. The transition
No
RDF = 1?
of the RDF flag from 0 to 1 can also be
identified by a receive FIFO data full
Yes
interrupt (RXI).
Read receive data in
SCFRDR, and clear RDF
[4]
flag in SCFSR to 0
No
All data received?
Yes
Clear RE bit in SCSCR to 0
[4] Serial reception continuation procedure:
To continue serial reception, read at least
the set receive trigger number of receive
data bytes from SCFRDR, read 1 from the
RDF flag, then clear the RDF flag to 0.
The number of receive data bytes in
SCFRDR can be ascertained by reading
SCFDR.
End of reception
Figure 22.15 Sample Flowchart for Receiving Serial Data (1)
Rev. 1.00 Sep. 19, 2007 Page 707 of 1136
REJ09B0359-0100