SH7730 Datasheet, PDF (478/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
CHCR
DMARS
RS[3:0] MID
RID
DMA
Transfer
Request
Source
DMA Transfer
Request Signal
1000
001011 01
SCIF3
TXI (transmit FIFO
transmitter data empty)
10 SCIF3
receiver
RXI (receive FIFO
data full)
001100 01
SCIF4
TXI (transmit FIFO
transmitter data empty)
10 SCIF4
receiver
RXI (receive FIFO
data full)
001101 01
SCIF5
TXI (transmit FIFO
transmitter data empty)
10 SCIF5
receiver
RXI (receive FIFO
data full)
001110 01
IrDA0
Transmit empty
transmitter transfer request
10 IrDA0
receiver
Receive full
transfer request
001111 01
IrDA1
Transmit empty
transmitter transfer request
10 IrDA1
receiver
Receive full
transfer request
010100 01
SIOF
TXI (transmit FIFO
transmitter data empty)
10 SIOF
receiver
RXI (receive FIFO
data full)
011010 11 ADC
ADI (A/D conversion
end)
101000 01
SIM
TXI (transmit FIFO
transmitter data empty)
10 SIM
receiver
RXI (receive FIFO
data full)
Source
Any
SCFRDR3
Any
SCAFRDR4
Any
SCAFRDR5
Any
IRIF0_UART4
Any
IRIF1_UART4
Any
SIRDR
ADDR
Any
SCRDR
Destination
SCFTDR3
Any
SCFATDR4
Any
SCAFTDR5
Any
IRIF0_UART3
Any
IRIF1_UART3
Any
SITDR
Any
Any
SCTDR
Any
Bus
Mode
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Rev. 1.00 Sep. 19, 2007 Page 430 of 1136
REJ09B0359-0100