SH7730 Datasheet, PDF (707/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
(6) 16-bit Stereo Data (3)
Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.1
used for right-channel data, slot No.2 used for control data for channel 0, slot No.3 used for
control data for channel 1, and frame length = 128 bits
1 frame
SIOFSCK
SIOFSYNC
SIOFTXD
SIOFRXD
L-channel R-channel Control Control
data
data channel 0 channel 1
Slot No.0 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7
1 bit delay
Specifications: TRMD[1:0] = 00 or 10, REDG = 0,
TDLE = 1,
TDLA[3:0] = 0000,
RDLE = 1,
RDLA[3:0] = 0000,
CD0E = 1,
CD0A[3:0] = 0010,
FL[3:0] = 1110 (frame length: 128 bits),
TDRE = 1, TDRA[3:0] = 0001,
RDRE = 1, RDRA[3:0] = 0001,
CD1E = 1, CD1A[3:0] = 0011
Figure 21.18 Transmit and Receive Timing (16-Bit Stereo Data (3))
(7) 16-bit Stereo Data (4)
Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.2
used for right-channel data, slot No.1 used for control data for channel 0 , slot No.3 used for
control data for channel 1, and frame length = 128 bits
1 frame
SIOFSCK
SIOFSYNC
SIOFTXD
SIOFRXD
L-channel Control R-channel Control
data
channel 0
data
channel 1
Slot No.0 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7
1 bit delay
Specifications: TRMD[1:0] = 00 or 10,REDG = 1,
FL[3:0] = 1110 (frame length: 128 bits)
TDLE = 1,
TDLA[3:0] = 0000, TDRE = 1,
TDRA[3:0] = 0010,
RDLE = 1,
RDLA[3:0] = 0000, RDRE = 1,
RDRA[3:0] = 0010,
CD0E = 1,
CD0A[3:0] = 0001, CD1E = 1,
CD1A[3:0] = 0011
Figure 21.19 Transmit and Receive Timing (16-Bit Stereo Data (4))
Rev. 1.00 Sep. 19, 2007 Page 659 of 1136
REJ09B0359-0100