SH7730 Datasheet, PDF (451/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
Section 12 Direct Memory Access Controller (DMAC)
This LSI includes the direct memory access controller (DMAC).
The DMAC can be used in place of the CPU to perform high-speed transfers between external
devices that have DACK (transfer request acknowledge signal), external memory, on-chip
memory, memory-mapped external devices, and on-chip peripheral modules.
12.1 Features
• Six channels (two channels can receive external requests)
• 4-Gbyte physical address space
• Data transfer unit is selectable: Byte, word (2 bytes), longword (4 bytes), 8 bytes, 16 bytes, and
32 bytes
• Maximum transfer count: 16,777,216 transfers
• Address mode: Dual address mode
• Transfer requests:
External request, on-chip peripheral module request, or auto request can be selected.
The following modules can issue an on-chip peripheral module request.
 SCIF0/1/2/3/4/5, IrDA0/1, SIOF, SIM, ADC, DAC, and CMT0/1/2/3/4
• Selectable bus modes:
Cycle steal mode (normal mode and intermittent mode) or burst mode can be selected.
• Selectable channel priority levels:
The channel priority levels are selectable between fixed mode and round-robin mode.
• Interrupt request: An interrupt request can be generated to the CPU after half of the transfers
ended, all transfers ended, or an address error occurred.
• External request detection: There are following four types of DREQ input detection.
 Low level detection
 High level detection
 Rising edge detection
 Falling edge detection
• Active level can be specified independently for the transfer request acknowledge signal
(DACK) and DMA transfer end signal (TEND).
Rev. 1.00 Sep. 19, 2007 Page 403 of 1136
REJ09B0359-0100