SH7730 Datasheet, PDF (516/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 14 Reset and Power-Down Modes
14.3.1 Standby Control Register (STBCR)
STBCR is a 32-bit readable/writable register that can select sleep mode and standby mode.
STBCR can be accessed only in longwords.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — STBY — — — — — — —
Initial value: 0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
R/W: R R R R R R R R R/W R R R R R R R
Initial
Bit
Bit Name Value R/W Description
31 to 8 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
STBY
0
R/W Standby
Executing the SLEEP instruction after this bit is set to 1
makes a transition to standby mode.
6 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Sep. 19, 2007 Page 468 of 1136
REJ09B0359-0100