SH7730 Datasheet, PDF (351/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
21
PMD
0
R/W Page Mode Specification for Byte-Selection SRAM
Specifies the page mode for byte-selection SRAM.
0: Non-page mode access
1: Page mode access
20
BAS
0
R/W Byte Access Selection for Byte-Selection SRAM
Specifies the WEn and RDWR signal timing when the
byte-selection SRAM interface is used.
0: Asserts the WEn signal at the read/write timing and
asserts the RDWR signal during the write access
cycle.
1: Asserts the WEn signal during the read/write access
cycle and asserts the RDWR signal at the write
timing.
19

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
18 to 16 WW[2:0] 000
R/W Number of Wait Cycles in Write Access
Specify the number of wait cycles necessary for write
access.
000: Same number of cycles set by WR[3:0] (read
access wait)
001: 0 cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Sep. 19, 2007 Page 303 of 1136
REJ09B0359-0100