 English |
|
|
|
|
|
|
|
| SH7730 Datasheet, PDF (1123/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series | |||
| |||
| ◁ |
Section 33 Electrical Characteristics
33.4.5 Burst ROM Timing
CKO
A25 to A0
CSn
RDWR
RD
T1
Tw
tAD1
tCSD1 tAS
tRWD1
tRSD
D15 to D0
Twx
T2B
Twb
T2B
tAD2
tAD2
tAD2
tCSD1
tRWD1
tRSD
tRDS3
tRDH3
tRDS3
tRDH3
WEn
BS
DACKn*
WAIT
tBSD
tBSD
tDACD
tWTH1
tWTH1
tDACD
tWTS1
tWTS1
Note: * Waveform when active low is specified for DACKn.
Figure 33.15 Read Bus Cycle of Burst ROM
(Software Wait 1, Asynchronous External Wait 1 Input, Burst Wait 1, Number of Burst = 2)
Rev. 1.00 Sep. 19, 2007 Page 1075 of 1136
REJ09B0359-0100
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese