SH7730 Datasheet, PDF (792/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
23.3.12 Transmit Data Stop Register (SCATDSR)
SCATDSR is an 8-bit readable/writable register that sets the number of data bytes to be
transmitted. This register is available when the TSE bit in SCAFCR is enabled. The transmit
operation stops after all data set by this register have been transmitted. Settable values are H'00 (1
byte) to H'FF (256 bytes). The initial value of this register is H'FF.
Bit: 7
6
5
4
3
2
1
0
TDSRD[7:0]
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7 to 0
Bit Name
TDSRD[7:0]
Initial
Value R/W
H'FF R/W
Description
Transmit Data Stop Setting
Rev. 1.00 Sep. 19, 2007 Page 744 of 1136
REJ09B0359-0100