SH7730 Datasheet, PDF (375/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Bit
5 to 3
2 to 0
Section 11 Bus State Controller (BSC)
Initial
Bit Name Value R/W Description
CKS[2:0] 000
R/W Clock Select
Select the clock input to count-up the refresh timer
counter (RTCNT).
000: Stop the counting-up
001: Bφ/4
010: Bφ/16
011: Bφ/64
100: Bφ/256
101: Bφ/1024
110: Bφ/2048
111: Bφ/4096
RRC[2:0] 000
R/W Refresh Count
Specify the number of continuous refresh cycles, when
the refresh request occurs after the coincidence of the
values of the refresh timer counter (RTCNT) and the
refresh time constant register (RTCOR). These bits can
make the period of occurrence of refresh long.
000: Once
001: Twice
010: 4 times
011: 6 times
100: 8 times
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Rev. 1.00 Sep. 19, 2007 Page 327 of 1136
REJ09B0359-0100