SH7730 Datasheet, PDF (327/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

The block diagram of the BSC is shown in figure 11.1.
Section 11 Bus State Controller (BSC)
BACK
BREQ
Bus
mastership
controller
CMNCR
WAIT
Wait
controller
CS0WCR
CS6BWCR
CS0, CS2,
CS3, CS4,
CS5A, CS5B,
CS6A, CS6B
MD5, MD3
A25 to A0,
D31 to D0
BS, RDWR, RD,
WE3 to WE0,
RAS, CAS,
CKE, DQMxx,
CE2A, CE2B
CE1A, CE1B
ICIORD, ICIOWR
IOIS16
REFOUT
Interrupt
controller
Area
controller
Memory
controller
Refresh
controller
RWTCNT
CS0BCR
CS6BBCR
SDCR
RTCSR
RTCNT
Comparator
RTCOR
BSC
[Legend]
CMNCR: Common control register
CSnWCR: CSn space wait control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
RWTCNT: Reset wait counter
CSnBCR: CSn space bus control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
SDCR: SDRAM control register
RTCSR: Refresh timer control/status register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
Figure 11.1 Block Diagram of BSC
Internal master
module
Internal slave
module
Rev. 1.00 Sep. 19, 2007 Page 279 of 1136
REJ09B0359-0100