SH7730 Datasheet, PDF (371/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
11.4.4 SDRAM Control Register (SDCR)
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — — — — — A2ROW[1:0] — A2COL[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R/W R/W R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — DEEP — RFSH RMODE PDOWN BACTV — — — A3ROW[1:0] — A3COL[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R/W R R/W R/W R/W R/W R R R R/W R/W R R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 21 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
20, 19
A2ROW 00
[1:0]
R/W Number of Bits of Row Address for Area 2
Specify the number of bits of row address for area 2.
00: 11 bits
01: 12 bits
10: 13 bits
11: Setting prohibited
18

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
17, 16 A2COL 00
[1:0]
R/W Number of Bits of Column Address for Area 2
Specify the number of bits of column address for area
2.
00: 8 bits
01: 9 bits
10: 10 bits
11: Setting prohibited
Rev. 1.00 Sep. 19, 2007 Page 323 of 1136
REJ09B0359-0100