SH7730 Datasheet, PDF (372/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
Bit
15, 14
13
12
11
10
9
Initial
Bit Name Value R/W

All 0 R
DEEP
0
R/W

0
R
RFSH
0
R/W
RMODE 0
R/W
PDOWN 0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Deep Power-Down Mode
This bit is valid for low-power SDRAM. If the RMODE
bit is set to 1 while this bit is set to 1, the deep power-
down entry command is issued and the low-power
SDRAM enters the deep power-down mode.
0: Self-refresh mode
1: Deep power-down mode
Reserved
This bit is always read as 0. The write value should
always be 0.
Refresh Control
Specifies whether or not the refresh operation of the
SDRAM is performed.
0: No refresh
1: Refresh
Refresh Control
Specifies whether to perform auto-refresh or self-
refresh when the RFSH bit is 1. When the RFSH bit is 1
and this bit is 1, self-refresh starts immediately. When
the RFSH bit is 1 and this bit is 0, auto-refresh starts
according to the contents that are set in RTCSR,
RTCNT, and RTCOR.
0: Auto-refresh is performed
1: Self-refresh is performed
Power-Down Mode
Specifies whether the SDRAM is entered in power-
down mode or not after the access to SDRAM is
completed. If this bit is set to 1, the CKE pin is pulled to
low to place the SDRAM to power-down mode.
0: Does not place the SDRAM in power-down mode
after access completion.
1: Places the SDRAM in power-down mode after
access completion.
Rev. 1.00 Sep. 19, 2007 Page 324 of 1136
REJ09B0359-0100