SH7730 Datasheet, PDF (309/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 10 Interrupt Controller (INTC)
10.3.11 NMI Flag Control Register (NMIFCR)
NMIFCR is a 16-bit register that has an NMI flag (NMIFL bit) that can be read and cleared by
software. The NMIFL bit is automatically set to 1 by hardware when the INTC detects an NMI,
and can be cleared by writing 0 through software.
The NMIFL bit does not affect CPU processing with regard to NMI acceptance. The NMI request
detected by the INTC is cleared when the CPU accepts it, but the NMIFL bit is not cleared
automatically. Even if 0 is written to the NMIFL bit before the CPU accepts the NMI request, the
NMI request is not canceled.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
NMIL — — — — — — — — — — — — — — NMIFL
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
Initial
Bit
Bit Name Value R/W Description
15
NMIL
0
R
NMI Input Level
Indicates the level of the signal input at the NMI pin.
This bit can be read to determine the NMI pin level. This
bit cannot be modified.
This bit operates in the same way as the NMIL bit in
ICR0.
0: NMI input level is low
1: NMI input level is high
14 to 1 —
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
NMIFL
0
R/W NMI Interrupt Request Detection
Indicates whether an NMI interrupt request signal has
been detected. This bit is automatically set to 1 when
the INTC detects an NMI interrupt request. Write 0 to
clear the bit. Writing 1 is ignored.
0: NMI interrupt request has not been detected
1: NMI interrupt request has been detected
Rev. 1.00 Sep. 19, 2007 Page 261 of 1136
REJ09B0359-0100