SH7730 Datasheet, PDF (333/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
Table 11.3 Address Space Map 2 (CMNCR.MAP[1:0] = B'01)
Physical Address
Area
Memory to be Connected
Capacity
H'00000000 to H'03FFFFFF Area 0
Normal memory
64 Mbytes
H'04000000 to H'07FFFFFF Area 1
Burst ROM (Asynchronous)
Internal I/O register area*³
64 Mbytes
H'08000000 to H'0BFFFFFF Area 2
Normal memory
64 Mbytes
Byte-selection SRAM
SDRAM
H'0C000000 to H'0FFFFFFF Area 3
Normal memory
64 Mbytes
Byte-selection SRAM
SDRAM
H'10000000 to H'13FFFFFF Area 4
Normal memory
64 Mbytes
Byte-selection SRAM
H'14000000 to H'17FFFFFF Area 5*²
Burst ROM (Asynchronous)
Normal memory
64 Mbytes
Byte-selection SRAM
H'18000000 to H'1BFFFFFF Area 6*²
PCMCIA
Normal memory
64 Mbytes
Byte-selection SRAM
H'1C000000 to H'1FFFFFFF Area 7
PCMCIA
Reserved area*¹
64 Mbytes
Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct
operation cannot be guaranteed.
2. For area 5, registers CS5BBCR and CS5BWCR are valid and CS5B is valid as the chip
select signal.
For area 6, registers CS6BBCR and CS6BWCR are valid and CS6B is valid as the chip
select signal.
3. Set the top three bits of the address to 101 to allocate in the P2 space.
Rev. 1.00 Sep. 19, 2007 Page 285 of 1136
REJ09B0359-0100