SH7730 Datasheet, PDF (231/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
The operation of the LDTLB instruction is shown in figure 7.16 and 7.17.
MMUCR
31
26 25 24 23
18 17 16 15
10 9 8 7
3210
LRUI
—
URB
—
URC
SV
—
TI — AT
Entry specification
SQMD
PTEH
31
10 9 8 7
0
VPN
—
ASID
PTEL
31 2928
10 9 8 7 6 5 4 3 2 1 0
—
PPN
— V SZ1 PR[1:0] SZ0 C D SH WT
Write
Entry 0
Entry 1
Entry 2
ASID [7:0] VPN [31:10] V
ASID [7:0] VPN [31:10] V
ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT
Entry 63 ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT
UTLB
Figure 7.16 Operation of LDTLB Instruction (TLB Compatible Mode)
Rev. 1.00 Sep. 19, 2007 Page 183 of 1136
REJ09B0359-0100