SH7730 Datasheet, PDF (717/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
22.3.3 Transmit Shift Register (SCTSR)
SCTSR is used to transmit serial data. The SCIF loads transmit data from SCFTDR into SCTSR,
then transmits the data serially from the TXD pin, LSB (bit 0) first. After transmitting one data
byte, the SCIF automatically loads the next transmit data from SCFTDR into SCTSR and starts
transmitting again.
The CPU cannot read from or write to SCTSR directly.
22.3.4 Transmit FIFO Data Register (SCFTDR)
SCFTDR is an 8-bit length16-stage FIFO register that stores data for serial transmission. When
data for transmission is written to SCFTDR while the transmit shift register (SCTSR) is empty, the
SCIF transfers the data written to SCFTDR to SCTSR and starts serial transmission. Continuous
serial transmission can be performed until there is no transmit data left in SCFTDR.
SCFTDR is write-only and cannot be read by the CPU. When SCFTDR is full (16 bytes), no more
data can be written. If writing of new data is attempted, the data is ignored.
Bit
7 to 0
Bit Name Initial Value R/W
SCFTD[7:0] Undefined W
Description
FIFO for serial transmit data
22.3.5 Serial Mode Register (SCSMR)
SCSMR is a 16-bit register that specifies the serial communication format of the SCIF and selects
the clock source for the baud rate generator.
The CPU can always read from and write to SCSMR.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — CA CHR PE OE STOP — CKS[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R/W R R/W R/W
Rev. 1.00 Sep. 19, 2007 Page 669 of 1136
REJ09B0359-0100