SH7730 Datasheet, PDF (434/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
If the BAS bit in CSnWCR is set to 1, the WEn pin and RDWR pin timings change. Figure 11.33
shows the basic access timing. In write access, data is written to the memory according to the
timing of the write enable pin (RDWR). The data hold timing from RDWR negation to data write
must be acquired by setting the HW[1:0] bits in CSnWCR. Figure 11.34 shows the access timing
when a software wait is specified.
CKO
A25 to A0
CSn
WEn
T1
T2
RDWR
Read _RD
D31 to D0
RDWR
Write RD
D31 to D0
High
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 11.32 Basic Access Timing for Byte-Selection SRAM (BAS = 0)
Rev. 1.00 Sep. 19, 2007 Page 386 of 1136
REJ09B0359-0100